1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method for calibrating optical-based metrology tools.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 11A of a semiconducting substrate or wafer 11 comprised of doped-silicon. In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. The substrate 11 may be doped with either N-type or P-type dopant materials, for example. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of manufacturing integrated circuit products, a variety of optical-based metrology tools, such as ellipsometers, scatterometry-based tools, reflectometers, optical gas emission analyzers, etc., are used to obtain a variety of different types of metrology data. Such metrology data may relate to the size of various features, the thickness of one or more layers of materials, the spacing between features, etc.
As a more specific example, during the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modern devices. The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Gate electrodes 14 may now be patterned to a width 12 that is approximately 180 nm, and further reductions are planned in the future, e.g., 120 nm. Since the width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational, even slight variations in the critical dimension 12 of the gate electrode 14 as fabricated may adversely affect device performance. Moreover, at a given level of a wafer, features, e.g., gate electrodes, may be formed to a variety of different critical dimensions. As another example, in manufacturing modem semiconductor devices, the thickness of various layers, e.g., gate insulation layers, is very tightly controlled such that completed devices may meet target performance specifications. For example, the thickness of the gate insulation layer 16 is very important in determining certain performance aspects of the completed transistor device. Thus, thickness measurements must, in some cases, be very accurate and very tightly controlled.
Given the importance of metrology data and tools in modem semiconductor device manufacturing, it is very important that the various metrology tools provide accurate, reliable data. Moreover, it is also important that the metrology tools be properly calibrated and maintained such that data derived through use of such metrology tools is accurate and reliable. Additionally, it is important to be able to monitor metrology processes performed in the metrology tool to determine when the process begins to degrade or drift. Such drift may be due to a variety of factors, such as the cleanliness of the tools, wear on various parts of the tool, etc.
The present invention is directed to various methods that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to various methods for calibrating optical-based metrology tools. In one illustrative embodiment, the method comprises performing a metrology process on a specimen using an optical-based metrology tool to obtain optical characteristic data and comparing the obtained optical characteristic data to target optical characteristic data established for the specimen.